The present invention concerns a management unit for a unit for switching data transmitted by asynchronous time-division multiplexing known as an ATD (Asynchronous Time Division) switching matrix. In this context the term "data" is to be understood in its widest sense encompassing information comprising speech, pictures and all kinds of data in the usual sense to be transmitted and switched through the integrated services digital network (ISDN).
In asynchronous time-division (ATD) transmission as understood in this context, the transmission medium of a transmission link is temporally divided into equal intervals each conveying one cell, meaning a group comprising a specific number of binary information units or bits, including a label containing a destination indication and a data field containing the communication information proper. The data rates of the tranmission link on current projects is in the order of several 100 megabits per second.
Switching consists in receiving digital information structured in this way from several input links and retransmitting the information on several output links. To be more precise, a cell received on one of the input links is retransmitted on one of the output links as designated by the destination indication contained in the cell.
A switching unit is a unitary device implementing switching of this kind between a defined number of input links and a defined number of output links. Switching units of this kind may be combined into a multistage switching network. In this case the destination indication must meet the requirements of each of the switching units passed through.
At a switching unit and in a stationary switching state the cells from one input link intended for the same output link constitute a data stream the average data rate of which is constant but the instantaneous data rate of which is subject to fluctuations that may be regarded as random. The cells retransmitted on an output link originate from several input links and represent the addition of several independent streams. The network control means must be such that the average data rate corresponding to this addition is at most equal to the transmission capacity of the output link if congestion is to be avoided. For reasons of efficiency, however, this average total data rate must also be able to approach as closely as possible the nominal transmission capacity of the link. This means that the sum of the instantaneous data rates will from time to time exceed the transmission capacity of the output link. Outside these peak periods this capacity will not be fully utilized.
Within a switching unit, the foregoing considerations lead to the provision of a buffer memory receiving the cells from the input links and storing them until they can be retransmitted on the output links.
A switching unit meeting the requirement as just defined is the subject of the French Pat. No. 2 538 976. This describes a switching unit for data transmitted by ATD multiplexing comprising receive circuits each associated with an input link and supplying cells received by that input link, transmit circuits each associated with an output link and sending retransmitted cells on that output link, a buffer memory storing received cells supplied by the receive circuits and delivering cells to be retransmitted to the transmit circuits, and a buffer memory addressing device including a write address source and a read address source.
On the receiving side, the received cells appear on an input bus leading to the buffer memory into which the received cells from the various input links are written cyclically. In parallel with this, the label of each cell is analysed by means of a control memory and supplies the address of the output link for which the cell is intended. This address designates a "first in--first out" (FIFO) memory associated with the output link. It makes it possible to write into the latter the address of the buffer memory location in which the cell in question has been written. The output FIFO memory of each output link therefore indicates where the cells to be retransmitted on that output link are to be read out from the buffer memory.
On the transmitting side, the output FIFO are interrogated cyclically. Each of them supplies, if it is not empty, the address of the location in the buffer memory in which is waiting the cell received longest ago and which is to be retransmitted on the associated output link. The buffer memory is read at this address. The cell read is supplied on an output bus and is fed to a transmit circuit by which it is transmitted on the output link.
The copending U.S. Pat. application No. 07/277,599 filed this day by the applicant under the title "Unit For Switching Data Transmitted By Asynchronous Time-Division Multiplexing" is directed to improving the efficiency of use of the buffer memory in a switching unit of the type that has just been described so that the size of the switching unit can be reduced or its performance can be improved.
The invention is based on the fact that among the cells transmitted on an output link, which is also an input link of a later switching stage, there are cells that must not or cannot be retransmitted. Most of these are "empty" cells. As already explained, outside peak periods the nominal transmission capacity for an output link is not filled by the sum of the data streams applied to it. There are therefore cells for which, initially, there is no communication information available. These cells are then filled with a configuration of bits which is highly unlikely to be reproduced by any communication cell. The benefit of transmitting empty cells of this kind is that it enables synchronization of the receive circuit with regard to the temporal subdivision into separate time intervals.
It is therefore proposed that the switching unit comprises a write disabling circuit conditioned by the contents of a receive cell or by the absence of any receive cell and supplying a disabling signal and in that the address source includes a disable port conditioned by said disabling signal whereby no memory location is then occupied in the buffer memory.
The address source may be a counter supplying the successive writing addresses in the buffer memory and the disabling circuits will then prevent incrementing of the counter, avoiding the use of a write location in the buffer memory.
The address source may include a memory storing addresses of buffer memory locations released by cells already retransmitted. Said disabling signal will then prevent the reading of an address in this address store, which will advantageously be a FIFO memory.
Cells not to be retransmitted will be identified in particular by a circuit for decoding the address part of the label. Identification may also be done by the receive circuit where it does not have any communication cell to supply, because it has received an empty cell or because a received cell is not ready at the time it should supply one or because the receive circuit is not functioning normally (desynchronized or out of order, for example).
These provisions also apply if the routing is of the self-directed type, in which case the label of each cell to be routed includes destination indications for each of the switching units to be passed through, or the virtual circuit type, in which case the destination indication included in the label of each cell to be routed has to be translated in each switching unit passed through.
The present invention is directed to providing an unit for switching data transmitted by asynchronous time-division multiplexing of the type described in the two documents mentioned with a management unit adapted to communicate with the input links and the output links of the switching unit even if the switching unit is faulty.
Generally speaking, a management unit of this kind is a logic device collecting information in the switching unit and receiving information on its input links to supply control signals to the switching unit and information on its output links.
A conventional way of connecting a management unit of this kind is to connect it to an output and to an input of the switching unit. It will immediately be understood that if the switching unit is faulty the management unit is deprived of access to the input and output links of the switching unit. Thus it cannot even send a message indicating the failure. Also, the management unit cannot communicate with the switching unit itself except through circuits installed specifically for this purpose and extending into the switching unit, which at the very least implies additional cost. This will be the case where the management unit has to supply information relating to traffic on the input and output links of the switching unit.
What is more, the documents FR-A- No. 2 526 613 and EP-A- No. 0 251 965 both describe a packet (or cell) switch comprising a control unit connected to the input bus and to the output bus of a switching matrix. However, in both cases it is a control unit intervening in the functioning of the switching matrix and which consequently has to receive all the cells appearing on the input bus or which must on its own initiative transmit cells on the output bus. Given these conditions, the input and output circuits of the management unit have to cater for the very high data rate of the cells on these buses, which makes them expensive or imposes a limit on this data rate.
The invention concerns a management unit which does not suffer any such penalty.